Typically microprocessors include an architecturally visible register that includes condition code flags that are used by conditional instructions, such as a conditional branch instruction or a conditional move instruction. For example, in the x86 instruction set architecture, the EFLAGS register contains the Carry Flag (CF), Parity Flag (PF), Auxiliary Carry Flag (AF), Zero Flag (ZF), Sign Flag (SF), and Overflow Flag (OF), which are condition code flags that may be used by conditional instructions, and which are well-defined on pages 3-20 to 3-23 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture, June 2006, which are hereby incorporated by reference in their entirety for all purposes. Examples of conditional instructions in the x86 architecture include the Jump If Condition Is Met (Jcc) instruction, the Conditional Move (CMOVcc) instruction, the Floating Point Conditional Move (FCMOVcc) instruction, the LOOPZ and LOOPNZ instructions, or the Set Byte on Condition (SETcc) instruction. Other instructions, i.e., an instruction earlier in program sequence to the conditional instruction, perform an arithmetic or logical operation to generate a result, and the microprocessor updates the condition code flags in the EFLAGS register based on the result. For example, a program may include a sequence of instructions that includes an ADD instruction followed later in the program by a JNZ instruction. The instruction set architecture specifies that the microprocessor updates the condition code flags in the EFLAGS register based on the result of the ADD instruction. For example, if the result of the ADD is zero, the microprocessor will set the ZF flag in the EFLAGS register. The JNZ instruction specifies a target address to which the microprocessor will jump if the ZF flag in the EFLAGS register is clear (i.e., not zero); otherwise, the microprocessor will fetch the next sequential instruction after the JNZ instruction.
Another feature of some modern microprocessors is that they include a microarchitecture that is different from the instruction set architecture, or architecture (also sometimes referred to as the macroarchitecture), of the microprocessor. This is typical of x86 architecture microprocessors. The architecture specifies the instruction set, register set, set of exceptions, and so forth that are visible to the assembly language programmer or compiler writer for the microprocessor. On the other hand, the microarchitecture specifies the internal organization of the microprocessor and includes details that are not visible in the architecture. For example, the microarchitecture specifies the various functional units of the microprocessor and their arrangement; whether the microprocessor is pipelined or non-pipelined, is scalar or superscalar, performs out-of-order execution, or performs speculative execution such as due to branch prediction and/or load hit prediction; the size and arrangement of cache memories; and so forth. Two different microprocessors may have the same architecture, yet have significantly different microarchitectures. In particular, in microprocessors that include microcode, the microarchitecture specifies its own instruction set that is different from the architecture instruction set and is typically not visible to the programmer. The instruction set of the microarchitecture is the set of instructions that the functional units of the microprocessor actually execute. The instructions of the architecture instruction set may be very complex and may be variable length. In contrast, the instructions of the microarchitecture instruction set typically are simpler than the instructions of the architecture instruction set, and popularly conform to the reduced instruction set computer (RISC) load-store and fixed instruction length paradigms. Furthermore, the number of registers of the microarchitecture register set is typically greater than the number of registers available in the architecture register set. For example, the microarchitecture may perform register renaming with its larger register set to improve performance.
Microprocessors that have distinct architectural and microarchitectural instruction sets include an instruction translator that translates architectural instructions (also referred to as macroinstructions) into instructions of the microarchitecture (microinstructions) that are dispatched to the execution units to be executed. Additionally, such microprocessors typically include microcode that implements some of the macroinstructions. The microcode is routines, or sequences, of microinstructions of the microarchitecture instruction set stored in a microcode memory of the microprocessor. When the instruction translator encounters a macroinstruction that is implemented in microcode, the instruction translator transfers control to a microsequencer, which fetches the microcode microinstructions from the microcode memory and dispatches them to execution units for execution. The microinstruction set includes instructions that update the architecturally-visible registers of the architecture in order to implement the macroinstructions. In particular, the microinstruction set includes instructions that update the architecturally-visible register that holds the condition code flags, such as the x86 EFLAGS register.
The present inventors have recognized that there are times when the microcode needs to include conditional instructions, such as conditional branch or conditional move instructions, that conditionally execute based on the results of arithmetic and logical instructions. For example, a microcode routine that implements a floating-point macroinstruction may include an arithmetic or logical microinstruction that generates an intermediate result followed by a conditional instruction that wants to know whether the intermediate result generated a carry or an overflow or a zero value or a negative or positive value, for example. However, the microcode cannot change the architectural condition code flags register unless the architecture specifies that the microcode-implemented macroinstruction updates the architectural condition code flags register, which is not true for many instructions of the x86 architecture, for example. For another example, a microcode exception handler may need to include an arithmetic or logical microinstruction that generates a result followed by a conditional instruction that wants to know a characteristic of the result such as those typically indicated by condition codes; however, the exception handler is not allowed by the architecture to update the condition code flags register of the architecture.
Therefore, what is needed is a microarchitecturally efficient means for the microinstructions of the microarchitecture instruction set to affect and examine condition code-like characteristics, without affecting the condition code flags of the architectural condition code flags register.